The present invention relates to logic circuits, and more particularly to a circuit for preserving state in a flip-flop during a power saving mode.
Most VLSI designs have numerous flip-flops integrated within them. Typically, flip-flops are critical to the overall performance of this design. Conventional flip-flops are generally large, power hungry and a significant amount of time is spent optimizing their configuration. It is desirable therefore to minimize the power used by flip-flops in a circuit design. In a flip-flop design, as technologies get smaller, it is harder to control the amount of leakage current provided thereby. Therefore, it is desirable to make device sizes smaller within the flip-flop at the same time being able to preserve the state of whatever contents are within the flip-flop. It is known that one way to save power is to shut off sections of the design. For example, one way to save power is to utilize clock gating to disable the clock when it is not used. Also, in an effort to save or minimize standby power, some designs have resorted to disabling non-used sections of the design from the power supply. However, disabling the power supply generally results in a loss of stored data in the volatile memory elements.
One solution for this problem is to transfer the data or state of the latch to an on-chip memory before the latch is disconnected from the power supply. Examples of chip memory include SRAM, DRAM or flash memory. This technique, however, requires an auxiliary device to preserve the state, which adds cost and adds to the overall size of the design of the device.
Accordingly, what is needed is a method and circuit for preserving data in a flip-flop while also conserving power. The method and circuit should also be cost effective, save space, and easily implemented in existing circuit designs. The present invention addresses such needs.
A flip-flop is disclosed in which power consumption is reduced in a standby mode. In a first aspect, the flip-flop comprises a first latch adapted to be coupled to a first power supply and a second latch coupled to the first latch and adapted to be coupled to a second power supply. The first and second power supplies are independently controllable to minimize power consumption in a standby mode.
In a second aspect, a flip-flop comprises a first latch adapted to be coupled to a first power supply. The first latch receives at least one bit. The flip-flop includes a second latch coupled to the first latch and adapted to be coupled to a second power supply. The second latch stores the at least one bit from the first latch. The size of the second latch is minimized to reduce power consumption. The flip-flop also includes a multiplexor coupled to the first latch and to the second latch for outputting the at least one bit from the first latch when a clock to the multiplexor is active and for outputting the at least one bit from the second latch when the clock is inactive. The first and second power supplies are independently controllable.
In a third aspect, a method for minimizing the power consumption of a flip-flop is also disclosed. The flip-flop includes a first latch and a second latch coupled thereto. The method comprises providing a first independently controllable power supply coupled to the master latch; and providing a second independently controllable power supply coupled to the slave latch. The method further includes reducing the voltage of at least one of the first and second power supplies responsive to the detection of a power saving mode.
An additional feature of the present invention is a restore mechanism which multiplexes the data and an output of a slave latch of a master/slave FF to enable recovery of the state of the contents of the master latch.
Finally, another feature of the present invention is a state latch which is coupled to the second power supply and is only activated upon detection of standby power saving mode to retain the contents of the master latch.
Hence, a simple means to optimize power consumption in random logic latch configurations with or without clock gating has been disclosed. According to the method and circuit disclosed herein, the present invention provides numerous benefits. For example, it preserves the data in a FF during a power savings mode.